Many applications demand high speed and cost effective computing solutions. As a result, many people are employing graphics processors and even field programmable gate arrays to accelerate their computations. Unfortunately, as architectures get faster and more power efficient, they also tend to get harder to program.
Many applications can be described as graphs where each node can be updated by operating on nearby nodes. My proposal is to design a configurable computing chip that operates by loading, updating, and storing nodes from a graph in memory. Such a design has the potential to be as efficient as an FPGA while being programmable with a simple abstraction like GraphLab.