This project focuses on test-set ordering for maximum diagnosis resolution in chip test data analysis. The aim of the project is to figure out an optimal algorithm for ordering test-sets in order to extract the most valuable information from the resulting test data, with the given test-sets. Thus, the goal is to examine whether ordering test-sets a certain way will contribute to diagnostic resolution improvement, along with various statistical and machine-learning techniques. The research will involve developing a brute-force solution based on examining all possible test sequences, carrying out complexity analysis, and testing for validating the utility of the re-ordered tests. Several tools will be utilized for this project, including ATALANTA, an automatic test pattern generator for stuck-at faults in combinational circuits, and HOPE, a fault simulator for synchronous sequential circuits. The project will also make use of EDA (Electronic Design Automation) tools and tests from actual ICs (Integrated Circuits).