The goal of this project is to begin work on building an FPGA implementation of an iris-recognition system with the help of Dr. Marios Savvides and under the advising of Dr. Don Thomas. Some current implementation approaches use software algorithms on commodity hardware which are both computationally and power intensive. Better approaches implement such algorithms on graphics cards, gaining performance by utilizing their parallel processing capabilities, but still consume a large amount of power. By implementing this algorithm on an FPGA, we expect to be able to perform complex computations at high speeds and have minimal power consumption. With this, iris-recognition systems can be more easily adapted for portable use-cases.
During the semester we will port portions of the algorithm to synthesizable hardware descriptions in SystemVerilog for the Zynq chip on the Zedboard development kit. For testing, we will construct test benches, also in SystemVerilog, to verify the correctness of each module in the iris-recognition algorithm.