Memory isolation is a key property of a reliable and secure computing system --- an access to one memory address should not have unintended side effects on data stored in other ad- dresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. After examining various potential ways of addressing the problem, we propose a new low-overhead solution to prevent the errors.
The things that I will contribute towards the project include the following: - Setting up a heat chamber to run experiments (this is required to simulate a longer period of time within shorter periods. We can claim this because we know DRAM cell retention time relations to heat. - Modifying RTL and drivers for the infrastructure so that we may be able to run different experiments given the existing RTL. - Running experiments and collecting data on a number of SO-DIMMs from multiple different companies. - Analyzing collected data with python and generating graphs for the ISCA paper given the new data sets.
We will attempt to determine the specific cause of disturbance errors and analyze to see whether there is a pattern in the occurrence of disturbance errors. With this knowledge we may be able to suggest a mechanism that will mitigate the problem.