Implementing LDPC Decoder for minimizing transmit + decoding power

Spring 2013

Patrick Jang
Pulkit Grover
Project description

The objective of this research project is to explore decoding power with different error correcting codes, focusing on the family of LDPC codes.

The method to be used is by creating a Verilog hardware description of the LDPC decoder and synthesizing it on to an FPGA and using different parity check matrices inputs to explore decoding power. The LDPC decoder will include descriptions of check nodes and variable nodes, and the wiring between the nodes will be determined on a case by case basis, based on the parity check matrix input. The actual Verilog files will be produced by a Unix bash shell script, which will take a parity check matrix input and degrees of connections. This will allow for testing of check matrices with differing dimensions.

The anticipated result is to determine that message encoding can be decreased for short-distance connections, and thus power can be saved by choosing the right error-correcting code.

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