Objectives: The current industry standard for transmitting and receiving data is currently consuming more power than necessary. Our research will attempt to find solutions to this problem by introducing more efficient error correcting codes: mainly the application of low density parity check (LPDC) codes as we analyse the trade-offs between decoding power consumption and reliability of the data transmission.
Methods: We will be building digital circuits that applies LPDC codes to the data received and analyze how much power is consumed through the whole process. First we will write a script that will generate the proper parameters (according to the parity-check matrix) for our digital circuit Verilog code. Our first decoder using the LPDC will be synthesized onto a FPGA.
Anticipated Results: It is expected that by using LPDC codes, the amount of total power needed to effectively transmit and decode/process the correct data will be significantly less than that of the industry norm.