A/D Converter

Spring 2013

Student
Chad Cole
Advisor
Rick Carley
Project description

The goal of this project is to explore the design space for an oversampled single-bit A/D converter that employs a form of mixed analog/digital loop unwinding in order to increase the operating speed of the converter. In particular, we are designing an oversampled A/D converter designed to sample a signal from DC-to-100 MHz with a dynamic range (SNDR) greater than 84dB. This will be achieved by employing a third-order noise shaping transfer function operating at an oversampling ratio of 32:1; i.e., operating at a clock rate of 6.4GS/s. At this extremely high sample rate, the comparators only have approximately 75ps to resolve the analog input voltage difference into a digital level. Even in advanced technologies like the 45nm SOI CMOS process we intend to employ in implementing the A/D converter, this is insufficient time for the comparator to reliably resolve the analog input into a digital level. By unwinding the loop and employing a mixed analog + digital loop strategy, we can allow the comparators up to 3 times longer (225ps) to resolve the analog input into a digital level without reducing the overall sampling rate. This represents an innovation on both the data converter architecture level and at the detailed circuit implementation level.

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