The goal of this project is to design a fully-working CPU on an FPGA. Our final design is expected to successfully implement the ARM instruction set and be fault-tolerant in the event of partial failure. By analyzing the ARM instruction set that is commonly used in modern-day electronics, we will design a data-path for the ISA and identify the function of all control points or signals needed by the data-path. Once the data-path for the ISA is completed, we will construct the logic of the primary control unit and map the ISA to the control unit in a logical way. The control unit should generate signals in the proper sequence, so that the control unit can successfully complete the instruction cycle to properly fetch, decode, and execute every instruction in its instruction set. After the completion of the control unit, the address path of CPU will be designed for easier access to the main memory (RAM) and to successfully read and write a large block of data. Following the completion of this project, our designed CPU is expected to be compatible with most modern day applications.