Develop a robust platform for simulation of the P18240 processor architecture. Simulation to be delivered to the students via a HTML5 standards-based browser, thus making this tool available across operating systems to local and remote users. Development of this tool will focus on methods to ensure the code is maintainable and thus easily modifiable to accommodate changes to the processor architecture, memory interface or user experience. A significant portion of this project will investigate visual methods to enhance student understanding of the P18240 datapath, such as animating data transfers, highlighting signaling pathways, and gradual value fades to allow for state change visibility.
