May 24, 2006
When Roland Wunderlich applies statistical measurement and modeling techniques to computer architecture, his simulations can have impact--for example, one project led to an Itanium central processing unit (CPU) model that was plugged into a computer system at Intel. The ECE graduate student and winner of an Intel Ph.D. Fellowship has already interned for Intel and IBM, and hopes to work with his new Intel award mentor to explore how high performance computing (HPC) software works on CPU designs. Let's catch up with Roland now:
Aberdeen, New Jersey
M.S. in ECE from Carnegie Mellon University, 2003, and B.S. in Computer Engineering from Rutgers University, 2001
Snowboarding and mountain biking.
James Hoe, Associate Professor of ECE and CS; Co-Director, Computer Architecture Lab at Carnegie Mellon (CALCM)
My research interests are focused on the application of statistical measurement and modeling techniques to computer architecture. The combination of these two disciplines is leading to a better understanding of microprocessor performance and new techniques for automated software tuning.
Today's CPUs have many complex mechanisms to accelerate program execution. My thesis research is focused on building fine-grain performance models of numerical software on real CPUs. In combination with the SPIRAL project, my goal is to refine a structured approach to generating the fastest numerical software for today's and tomorrow's computer systems.
Yes, I have worked with Intel Research Pittsburgh for my class research project in 18-843, Mobile Computing Systems & Applications, in Fall 2003. My group worked with Dr. Michael Kozuch from Intel Research Pittsburgh on our project entitled "Surrogate Discovery for Data Staging." Our project developed a method to select the nearest computers on the Internet by triangulating a relative position with just a few network measurements.
My teaching internship was a great experience, and I am excited about teaching again in the future. In fact, my last teaching internship followed my summer internship at Intel, and I remember several times being able to give real-world examples to the students based on my work at Intel.
I am looking forward to collaborating with researchers at Intel. My research can benefit directly from interaction with Intel about my performance modeling of existing Intel CPUs, and with predictions of how high performance computing (HPC) software will work on future CPU designs.
My most challenging publication was definitely my Itanium FPGA [Field Programmable Gate-Array] paper in ICCD [International Conference on Computer Design] 2004. It was almost one and a half years of work that led up to a working Itanium CPU model that was actually plugged into a working computer system at Intel.
The most widely known and cited work of mine stems from a class project my first semester at CMU. The SMARTS [Sampling Microarchitecture Simulation framework] paper (in ISCA [International Symposium on Computer Architecture] 2003) begun when Thomas Wenisch and I worked together on our class research project, and has resulted in several publications over the past several years.
I am still considering my career options following my graduation, but I am most interested in working at an industrial research lab. My training at CMU has taught me how to attack the most complex engineering problems in a systematic way. In addition, my work on functioning prototypes and real world computer systems (beyond mere simulations) has given me invaluable hands-on experience.
