Blanton and Dwarakanath Awarded Patent


March 14, 2005

ECE Professor Shawn Blanton and alumnus Kumar Dwarakanath (Ph.D. 2004) were awarded a patent for their "Method for Characterizing, Generating Test Sequences for, and/or Stimulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products."

Dwarakanath's thesis on the fault tuples simulator (FATSIM) was nominated by Carnegie Mellon for the 2004 Association for Computing Machinery (ACM) Doctoral Dissertation Award.

"Fault tuples represent a general methodology for analyzing failures in integrated circuits (ICs)," explained Blanton. "The key characteristic is the capability to precisely model the effects of arbitrary defects on the logical behavior of a circuit. Fault simulation, test generation and diagnostic CAD tools based on fault tuples enable test programs to be customized for a given design and fabrication technology."

Their research is associated with the Carnegie Mellon Laboratory for Integrated Systems Test (CM-LIST) and the Center for Silicon System Implementation (CSSI).

Fault coverage results produced by the fault tuple simulator (FATSIM) for an example circuit.

Related People:

Ronald Blanton

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