Leveraging Network Technology for Power-Efficient Computer Architecture

ECE Seminar: Leveraging Network Technology for Power-Efficient Computer Architecture

Starts at: September 24, 2015 4:30 PM

Ends at: 6:00 PM

Location: Scaife 125

Speaker: Dr. Jiang Hu

Affiliation: Texas A&M University

Refreshments provided: Yes

Link to Poster

Link to Video (1)


The fundamental limit of chip power density has been and continues to be a
grand challenge to the silicon-based computing technology. This talk presents
a new approach to processor power management that leverages network
technology. In modern chip multiprocessors, resources shared by processor cores, such as on-chip communication and shared memory, play an increasingly critical role in determining the overall performance. Our key observation is that per-core dynamic voltage/frequency scaling (DVFS) can be used as a client regulation mechanism for Quality-of-Service (QoS) of the shared resources. As a result, power savings are feasible with little performance loss or even performance gain due to the better allocation of shared resources. Based on this
observation, we propose a new DVFS technique based on TCP Vegas, a congestion control protocol from the networking domain. We also propose an uncore (communication + last level cache) DVFS technique that is applied in
conjunction with the QoS-driven core DVFS. For single- application cases, our
techniques achieve 53% energy savings with less than 1% performance
degradation on average. Some applications actually show a small performance
improvement while still saving significant energy, indicating the power of
utilizing DVFS as a means of QoS. We demonstrate that these results also hold
for multi-application workloads.

Jiang Hu received the B. S. degree in optical engineering from Zhejiang
University, China, in 1990, the M. S. degree in physics in 1997, and the Ph.
D. degree in electrical engineering from the University of Minnesota in 2001.
He was with IBM Microelectronics from January 2001 to June 2002.
Currently, he is a professor in the Department of Electrical and Computer Engineering at the Texas A&M University. His research interests include large scale optimization, low power system design, design for robustness/reliability, hardware acceleration for machine learning and hardware security.
He received a best paper award at the ACM/IEEE Design Automation Conference in 2001, an IBM Invention Achievement Award in 2003 and a best paper award at the IEEE/ACM International Conference on Computer-Aided Design in 2011. He has served as technical program committee member for DAC, ICCAD, ISPD, ISQED, ICCD, DATE, ASPDAC, ISLPED and ISCAS, technical program chair and general chair for the ACM International Symposium on Physical Design, and associated editor for IEEE Transactions on CAD and ACM Transactions on Design Automation of Electronic Systems.