Vanessa Chen Defense

Vanessa Chen Defense


Starts at: November 25, 2013 10:00 AM

Ends at: 1:00 PM

Location: HH 2117

Details:

The demand for fast-speed and high-capacity advanced network services, such as wireless high-definition video links, multi-gigabits/s wireless data transfer, multimedia-on-demand, and cloud computing, is fueling the progress of communication systems to higher data rates. The biggest implementation challenge for these advanced communication systems is the need for ultra-high-speed ADCs, particularly while the ADCs are required to integrate on a single chip with the backend digital signal processing (DSP), such as a central processing unit (CPU) and a graphics processing unit (GPU). Such applications usually require ADCs to achieve the signal-to-noise-and-distortion-ratio (SNDR) of over 20 dB while operating at multi-gigahertz. To achieve these levels of resolution requires up-sized transistors that result in ADCs that occupy a large area and dissipate significant power. Therefore, the power constraints of such communication systems require ADCs to achieve low power consumption while providing sufficient resolution bandwidth.

To reach the high data rates required by these communication systems, flash and time-interleaved ADCs are utilized so as to achieve more parallelism. In order to obtain better power efficiency while operating at high speed, in this work small-size transistors are used in comparators and clock delivery circuits to avoid serious noise coupling and save considerable power. The non-ideal effects due to mismatch in high-speed ADCs are then corrected by the presented calibration algorithms and design techniques. For flash ADCs, large comparator offsets due to random mismatch are calibrated with the dynamic offset calibration, particularly for the parasitic capacitor mismatch that impacts on high-speed ADC performance. The calibration algorithm is based on application of statistical element selection (SES) that uses combinatorial redundancy to exploit the random process mismatch to reduce comparator offsets. The method effectively characterizes the comparators at full speed to compensate for the dynamic mismatch errors that occur during high speed operation. For time-interleaved ADCs, the presented background calibration scheme uses an embedded time-to-digital converter to detect timing skew and compensates for the clock misalignment between channels with the aligning buffers.

Two proof-of-concept prototype ICs were designed and implemented in IBM’s 32nm CMOS SOI process. The first one is an 8.5mW 5-GS/s 6-bit flash ADC with the aforementioned dynamic offset calibration. The flash ADC achieves an SNDR of 30.9dB at Nyquist and consumes 8.5mW with an FOM of 59.4fJ/conv-step. The second one is a 69.5mW 20-GS/s 6-bit 8-way time-interleaved ADC based on the on-chip background calibration that consists of the dynamic offset calibration and the embedded time-to-digital calibration described above to reduce gain, offset, and delay mismatches between channels. The time-interleaved ADC with the low-complexity calibration achieves an SNDR of 30.7 dB at Nyquist and consumes only 69.5mW with an FOM of 123.9fJ/conv-step. The measurement results show that the presented designs achieve the best reported power consumption and figure of merit for high-speed ADCs with over 5GS/s sampling rates.