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With process technologies scaling into the nanometer regime, the underlying implementation technology increasingly affects architecture and circuit design. We must adapt and reinvent current designs to circumvent technology constraints (e.g. interconnect delay, device leakage, soft-errors, device mismatch) and to target emerging applications (e.g. sensor networks, computational biology). The key near-term challenge is to build compute systems that can efficiently achieve high-performance, yet remain economically feasible, general-purpose, and easy to program. In the long-term, with CMOS scaling approaching fundamental limits, the challenge will be to build efficient, high-performance, reliable computation systems from technology building blocks that may be radically different from those we use today.
My primary research interest is the circuit design of efficient, high-performance digital blocks (i.e. memories and functional units) in future generation technologies. Further, I'm interested in building tools to export VLSI-level design information and constraints to architectural-level design.
Carnegie Mellon, 2005
Digital circuit design, computer architecture, memory design, reconfigurable computing