| Department | Electrical and Computer Engineering |
|---|---|
| babak.falsafi@epfl.ch | |
| Website | http://www.ece.cmu.edu/~babak/ |
Prof. Falsafi's research group, Impetus, focuses on the design, evaluation, and implementation of computer systems with emphasis on processor and memory architecture. Current projects include:
While memory capacity in recent years has increased commensurately with processor speeds, memory speeds have primarily lagged behind. The brute-force approach of building a hierarchy of storage elements — i.e., caches — trading off size for speed at every level has reached diminishing returns. A STEMS system extracts repetitive spatially- and temporally-correlated streams of instruction/data corresponding to computational fragments, and speculatively moves them among processors prior to use and away upon completion of reuse to bridge the processor/memory performance gap.
The continued scaling of CMOS processes and circuits will result in unprecedented low levels of chip reliability due to a number of error sources including but not limited to transient (soft) error — resulting from shrinking devices and increased vulnerability to cosmic radiation, gradual error — due to the increase in device performance variability, and wear-out error — due to degradation of devices over time. We are exploring the design space for architectural support to detect and recover from error in future gigascale CMOS designs in both single-chip and scalable computer systems.
Computer architects have long relied on software simulation to measure dynamic performance metrics (e.g. CPI) of a proposed design. Unfortunately, with the ever-growing size and complexity of modern hardware platforms, detailed software simulators have become prohibitively (e.g., > 1000000x) slower than their hardware counterparts. We are exploring simulation methodologies and frameworks for fast, yet accurate and flexible full-system simulation of large-scale computer systems. Our frameworks rely on statistical sampling to provide accuracy and speed, and componentization to provide flexibility.

Carnegie Mellon, 2001
Computer Systems
Computer architecture, memory systems, multiprocessor architecture, architectural support for gigascale integration, design evaluation tools
PhD, 1998
Computer Science
University of Wisconsin, Madison
MS, 1992
Computer Science
University of Wisconsin, Madison
BS, 1990
Electrical and Computer Engineering
SUNY at Buffalo
BS, 1990
Computer Science
SUNY at Buffalo