18-760: VLSI CAD: Logic to Layout

Units: 12

A large digital integrated circuit (IC) may require 100,000 lines of high-level description in a hardware modeling language, which then turns into 1,000,000 logic gates, which ultimately end up as 100 million polygons on the masks that define the IC.

This course opens up the important CAD tools that perform the many steps of the transformation from Boolean equations to masks. We focus on mathematical models, algorithms, and data structures. We will write programs for simple versions of these tools. We will look at, and experiment with, a few real tools.

We begin with a review of Boolean algebra, but from a computational viewpoint you don't see when you do Karnaugh maps by hand. We then move on to look at synthesis tools for 2-level and multi-level logic, that transform Boolean equations and finite state machine descriptions into optimized logic, and verification tools that decide whether the logic you built does the same thing as the specification you started with. We look at geometric layout synthesis tools for component partitioning, placement, and wire routing.We look at geometric layout verification tools that decide if you satisfied the manufacturing design rules, that extract back the circuit from all those polygons.

Course grade is based on homework assignments (about 5-6), paper reviews (2), and projects (1-2 smaller warm-up projects, and then 1 significant group design project that allows creative input from the students.)

4 hrs. lec.

Prerequisites: 15-214 and 18-240 and 18-320


Computer Hardware, Computer Hardware Engineering


Last modified on 2006-03-14



Past semesters:

S14, S13, S12, S11, F09, F08, F06, F05, F04, F03, F02, F01, F00, F99