Course Information

18-760: VLSI CAD: Logic to Layout




A large digital integrated circuit (IC) may require 100,000 lines of high-level
description in a hardware modeling language, which then turns into 10,000,000 logic gates, which ultimately end up as 1 billion polygons on the

masks that define the integrated circuit. This course describes in detail the important CAD tools that perform the many steps of the transformation from Boolean equations to fabrication masks. We focus on mathematical models, algorithms, and data structures. We will write programs for simple versions of these tools. We will look at, and experiment with, a few real tools. The course covers a review of Boolean algebra, followed by (i) synthesis tools for 2-level and multi-level logic, that transform Boolean equations and finite state machine descriptions into optimized logic, and (ii) verification tools that decide whether the logic you built does the same thing as the specification you started with. Finally, the course covers geometric layout synthesis tools for component partitioning, placement, and wire routing and timing verification tools that determine if performance constraints are met. The CAD algorithms covered in the lectures are applicable not only to VLSI systems, but also to non-silicon applications (e.g., social computing, biology, financial).

Prerequisites: 15-214 and 18-240 and 18-320

Last Modified: 2006-03-14 4:10PM

Semesters offered:

  • Spring 2015
  • Spring 2014
  • Spring 2013
  • Spring 2012
  • Spring 2011
  • Fall 2009
  • Fall 2008
  • Fall 2006
  • Fall 2005
  • Fall 2004
  • Fall 2003
  • Fall 2002
  • Fall 2001
  • Fall 2000
  • Fall 1999