The first portion of the course will review the status of 3D system integration and will analyze potential benefits and shortcomings of the current vision of the 3D integration. Manufacturability of 3D systems will be analyzed and a number of potential stumbling blocks will be identified. Two of them, low yield and poor testability, will be discussed in detail. The cost and performance penalties associated with the application of Through Silicon Vias (TSVs) will be assessed. The second portion of the course will focus an alternative 3D integration paradigm that is based on new transistor architecture named VeSFET (Vertical Slit FET). Instruction will be supplemented by in-class student presentation of key papers in the area. Unpublished materials will also be presented by the Instructor.
Prerequisite: Graduate Standing