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 ======  ======
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+As FPGAs are changing in terms of their incorporation into the computing landscape, so have our views of the CoRAM architecture and abstraction. Recently we have added [[https://users.ece.cmu.edu/~jhoe/distribution/2015/fpl2015.pdf|CoRAM++]] to support data-structure-specific memory interfaces for FPGA computing and are actively working towards incorporating shared-memory processor-FPGA systems into the CoRAM abstraction. A new website is under construction to showcase our recent and ongoing CoRAM efforts. In the mean time, this site is still active for those who would like to explore our CoRAM "Classic" reconfigurable computing abstraction.
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 To address these limitations, the **Connected RAM (CoRAM) memory architecture** is an endeavor to standardize and simplify how FPGA computing applications interact with memory and I/O, which is a critical step towards a portable FPGA abstraction.  CoRAM presents a programmable, customizable view of memory that can be retargeted to different devices and platforms (see Figure, right).  The abstraction modifies the traditional FPGA's on-die SRAMs to act as in-fabric distributed portals to off-chip memory and I/O.  A salient feature of CoRAM is the ability to program these customizable, on-die SRAMs using a software control thread that is portable and easy-to-use.  Compared to the traditional approach where the FPGA memory hierarchy and I/O sub-system is hand-built at the RTL-level for each application, the CoRAM memory architecture can be used to efficiently support a broad range of applications.
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+{{ http://www.youtube.com/v/fbzniv5nuNg?.swf?400x333 }}
 ===== People =====
 **Faculty:** [[http://www.ece.cmu.edu/~jhoe|James C. Hoe]], [[http://www.ece.cmu.edu/directory/details/298/|Ken Mai]]\\
-**Students:** [[http://www.ece.cmu.edu/~echung|Eric S. Chung]],  [[http://www.cs.cmu.edu/~mpapamic|Michael K. Papamichael]], [[http://www.cs.cmu.edu/~gweisz|Gabriel Weisz]], Cagla Cakir, Yu Wang
+**Students:** [[http://www.ece.cmu.edu/~echung|Eric S. Chung]],  [[http://www.cs.cmu.edu/~mpapamic|Michael K. Papamichael]], [[http://www.cs.cmu.edu/~gweisz|Gabriel Weisz]], Cagla Cakir, Yu Wang, Marie Nguyen, Joseph Melber
-===== Funding =====
+===== Acknowledgments =====
-This work is supported by the [[http://www.nsf.gov|National Science Foundation]] (CCF-1012851).
+Funding for this work is provided, in part, by the National Science Foundation (CCF-1012851) and by Altera.  We thank Altera and Xilinx for their donation of tools and hardware.
 ===== Related =====
-**{{http://www.ece.cmu.edu/calcm/carl2010|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010)}}**
+**[[graphgencnn|Convolutional Neural Network Demo using the GraphGen compiler and CoRAM back end]]**
+**{{http://www.ece.cmu.edu/calcm/carl|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013)}}**
+**{{https://github.com/shtaxxx/PyCoRAM|PyCoRAM - A Python-based Implementation of the CoRAM Memory Architecture.}}**
+**{{http://www.ece.cmu.edu/~calcm/carl/doku.php?id=wiki:carl2012|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2012)}}**
+**{{http://www.ece.cmu.edu/~calcm/carl/doku.php?id=wiki:carl2010|Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010)}}**
 ===== Affiliations =====
 **{{http://www.ece.cmu.edu/~calcm|Computer Architecture Lab at Carnegie Mellon}}**\\
 **{{http://www.nsf.gov|National Science Foundation}}**
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