Overview

In the quest for energy-efficient computing, Field Programmable Gate Arrays (FPGAs) have emerged as a class of general-purpose accelerators with significant potential for addressing the increasing demands for performance while reducing energy consumption simultaneously. Despite their raw capabilities, today's commodity FPGAs are impractical as general-purpose computing devices. When developing an application for an FPGA, designers are often confronted by: (1) low-level, error-prone hardware description languages (HDL), (2) ``bare-bones'' fabric with nothing but a sea of logic and I/O pins, and (3) low-level, vendor-specific interfaces and gateware that the application must be made compatible with.

To address these limitations, the Connected RAM (CoRAM) memory architecture is an endeavor to standardize and simplify how FPGA computing applications interact with memory and I/O, which is a critical step towards a portable FPGA abstraction. CoRAM presents a programmable, customizable view of memory that can be retargeted to different devices and platforms (see Figure above). The abstraction modifies the traditional FPGA's on-die SRAMs to act as in-fabric distributed portals to off-chip memory and I/O. A salient feature of CoRAM is the ability to program these customizable, on-die SRAMs using a software control thread that is portable and easy-to-use (see Figure, right). Compared to the traditional approach where the FPGA memory hierarchy and I/O sub-system is hand-built at the RTL-level for each application, the CoRAM memory architecture can be used to efficiently support a broad range of applications.

Faculty: James C. Hoe, Ken Mai
Students: Eric S. Chung, Michael K. Papamichael, Gabriel Weisz, Cagla Cakir, Yu Wang

This work is supported by the National Science Foundation (CCF-1012851).

Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010)

Computer Architecture Lab at Carnegie Mellon
National Science Foundation