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There have been ample successful examples of applying Xilinx Vivado's “function-to-module” high-level synthesis (HLS) where the subject is algorithmic in nature. In CONNECT-HLS project, we carried out a design study to assess the effectiveness of applying Vivado-HLS in structural design, where precise bit- and cycle- level control is a must. We succeeded in using Vivado-HLS to produce router and NoC modules that are exact cycle- and bit-accurate replacements of our reference CONNECT RTL-based router and NoC modules. The routers and NoCs resulting from HLS and RTL are comparable in resource utilization and critical path delay. Our experience subjectively suggests that HLS is able to simplify the design effort even though much of the structural details had to be provided in the HLS description through a combination of coding discipline and explicit pragmas.

For more details, please see our technical report and source code which will be sent as an attachment to the provided email address. Beside the illustrative code examples in technical report, we also provide complete router C++ source code. CONNECT Network-on-Chip Generator