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hls_router [2017/02/22 16:13] zzhao1 |
hls_router [2017/02/23 07:53] (current) zzhao1 |
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| + | There have been ample successful examples of applying Xilinx Vivado's "function-to-module" high-level synthesis (HLS) where the subject is algorithmic in nature. In CONNECT-HLS project, we carried out a design study to assess the effectiveness of applying Vivado-HLS in structural design, where precise bit- and cycle- level control is a must. We succeeded in using Vivado-HLS to produce router and NoC modules that are exact cycle- and bit-accurate replacements of our reference [[http://users.ece.cmu.edu/~mpapamic/connect|CONNECT]] RTL-based router and NoC modules. The routers and NoCs resulting from HLS and RTL are comparable in resource utilization and critical path delay. Our experience subjectively suggests that HLS is able to | ||
| + | simplify the design effort even though much of the structural details had to be provided in the HLS description through a combination of coding discipline and explicit pragmas. | ||
| + | For more details, please see our technical report and source code below. Please contact [[zzhao1@andrew.cmu.edu|Zhipeng Zhao at zzhao1@andrew.cmu.edu]] | ||
| + | for any questions or bug reports. | ||
| <html> | <html> | ||
| - | <body onLoad="FireOffAJAXRequest();"> | + | <font size=4><b>Technical Report</b></font> |
| - | <font size=4><b>Step 2: Select Hardware Options</b></font> | + | <hr> |
| + | </html> | ||
| - | <form name="corform" action="coram.php" method="post" onSubmit="redirectOutput(this)"> | + | **{{http://www.ece.cmu.edu/~coram/connect-hls/Tech_Report.pdf|Using Vivado-HLS for Structural Design: a NoC Case Study}}**\\ |
| - | <table cellspacing="4" cellpadding="4"> | + | \\ |
| - | <tr> | + | |
| - | <td>Network-on-Chip</td> | + | |
| - | <td width="10"></td> | + | |
| - | <td><select name="topology"> | + | |
| - | <option value="xbar">Crossbar</option> | + | |
| - | </select> | + | |
| - | </td> | + | |
| - | </tr> | + | |
| - | <tr> | + | <html> |
| - | <td>User Clock</td> | + | <font size=4><b>Source Code</b></font> |
| - | <td></td> | + | <hr> |
| - | <td><select name="clock"> | + | </html> |
| - | <option value="100">100MHz</option> | + | |
| - | </select> | + | |
| - | </td> | + | |
| - | </tr> | + | |
| - | <tr> | + | We provide the C++ source code for both illustrative examples in technical report and a fully parameterized router. The code is only intended for internal, non-commercial research use and released under {{http://www.ece.cmu.edu/~coram/connect-hls/LICENSE|MIT License}}. |
| - | <td>Platform</td> | + | |
| - | <td></td> | + | |
| - | <td><select name="spec"> | + | |
| - | <option value="ml605sim">Simulation-only</option> | + | |
| - | <option value="ml605">Xilinx ML605 Board</option> | + | |
| - | <option value="de4">Altera DE4 Board</option> | + | |
| - | </select> | + | |
| - | </td> | + | |
| - | </tr> | + | |
| - | </table> | + | <html> |
| - | + | ||
| - | <font size=4><b>Useful definition files</b></font> | + | |
| - | <font size=3> | + | |
| - | <ul> | + | |
| - | <li> <a href="doku.php?id=coram_files">Description of these files</a> | + | |
| - | <li> <a href="coram-examples/cpi.h">CoRAM Control Thread Programming Interface</a> | + | |
| - | <li> <a href="coram-examples/Coprims.v">CoRAM Black Box Modules (Verilog)</a> | + | |
| - | </ul> | + | |
| - | </font> | + | |
| - | + | ||
| - | + | ||
| - | <br> | + | |
| - | <font size=4><b>Step 3: Enter Control Thread Program Description</b></font> | + | |
| - | <br><br> | + | |
| - | + | ||
| - | <table> | + | |
| - | <tr> | + | |
| - | <td>Or select an existing design:</td> | + | |
| - | <td width="10"></td> | + | |
| - | <td><select name="template" onchange="FireOffAJAXRequest();"> | + | |
| - | <!-- none removed because it fails to compile (GW) <option value="none"></option> --> | + | |
| - | <option value="simple">Simple Design with single 1024x32 CoRAM</option> | + | |
| - | <option value="mvm0">Matrix-Vector Multiplication (Naive)</option> | + | |
| - | <option value="mvm1">Matrix-Vector Multiplication (Loop-reorder)</option> | + | |
| - | </select> | + | |
| - | </td> | + | |
| - | </tr> | + | |
| - | </table> | + | |
| - | + | ||
| - | <!-- Textarea populates from onload now --> | + | |
| - | <textarea style="background: #556B2F; font-family: Consolas, Arial, sans-serif; font-size: 14px; color: #ffffff; border:none; padding:16px; width:96%; height:450px" id="ctrl" name="ctrl" onkeydown="return catchTab(this,event)"> | + | |
| - | </textarea> | + | |
| - | + | ||
| - | <br><br> | + | |
| - | <font size=4><b>Step 4: Enter Core Logic in Verilog</b></font> | + | |
| - | <br><br> | + | |
| - | + | ||
| - | <textarea style="background: #303030; font-family: Consolas, Arial, sans-serif; font-size: 14px; color: #ffffff; border:none; padding:16px; width:96%; height:450px" id="user" name="user" onkeydown="return catchTab(this,event)"> | + | |
| - | </textarea> | + | |
| - | + | ||
| - | <br><br> | + | |
| - | <font size=4><b>Step 5: Generate Design</b></font> | + | |
| - | <br><br> | + | |
| - | <font face="Courier New" size=2> | + | |
| - | The generated Verilog files and scripts from this website are for internal, non-commercial, academic research use only and is not for redistribution, with or without modifications. You may not use the name "Carnegie Mellon University" or derivations thereof to endorse or promote products derived from this software. | + | |
| - | <br><br> | + | |
| - | THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY, CONTRACT, TORT OR OTHERWISE). | + | |
| - | </font> | + | |
| - | <br><br> | + | |
| + | <form name="corform" action="connect-hls.php" method="post" onSubmit="redirectOutput(this)"> | ||
| <table> | <table> | ||
| Line 110: | Line 46: | ||
| - | <input style="height: 30px" id="submit" name="submit" type="submit" value=" I agree to the terms above. "/> | + | <input style="height: 30px" id="submit" name="submit" type="submit" value=" Get Source Code "/> |
| </form> | </form> | ||
