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Step 2: Select Hardware Options
Network-on-Chip
Crossbar
User Clock
100MHz
Platform
Simulation-only
Xilinx ML605 Board
Altera DE4 Board
Useful definition files
Description of these files
CoRAM Control Thread Programming Interface
CoRAM Black Box Modules (Verilog)
Step 3: Enter Control Thread Program Description
Or select an existing design:
Simple Design with single 1024x32 CoRAM
Matrix-Vector Multiplication (Naive)
Matrix-Vector Multiplication (Loop-reorder)
Step 4: Enter Core Logic in Verilog
Step 5: Generate Design
The generated Verilog files and scripts from this website are for internal, non-commercial, academic research use only and is not for redistribution, with or without modifications. You may not use the name "Carnegie Mellon University" or derivations thereof to endorse or promote products derived from this software.
THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY, CONTRACT, TORT OR OTHERWISE).
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hls_router.1487780038.txt.gz
· Last modified: 2017/02/22 16:13 by
zzhao1
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