Write your control thread description below:
#include <cpi.h> ctrl_thread() { }
Write your user core logic below:
module top(CLK, RST_N); input CLK, RST_N; endmodule
Hardware Configuration:
Core Logic HDL:
Verilog 95
User Clock:
100MHz
Platform:
Xilinx ML605 Board
Convey HC-1
Xilinx XUPv5
BEE3 (Single-FPGA)
Email: