Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures
Tuesday November 30, 2004
Hamerschlag Hall D-210
This is a practice talk for the upcoming IEEE
Micro conference, December 4-8.
Carnegie Mellon University
Previous proposals for soft-error tolerance have called for redundantly
executing a program as two concurrent threads on a superscalar microarchitecture.
In a balanced superscalar design, the extra workload from redundant
execution induces a severe performance penalty due to increased
contention for resources throughout the datapath. This paper identifies
and analyzes four key factors that affect the performance of redundant
execution, namely 1) issue bandwidth and functional unit contention,
2) issue queue and reorder buffer capacity contention, 3) decode
and retirement bandwidth contention, and 4) coupling between redundant
threads' dynamic resource requirements. Based on this analysis,
we propose the SHREC microarchitecture for asymmetric and staggered
redundant execution. This microarchitecture addresses the four factors
in an integrated design without requiring prohibitive additional
hardware resources. In comparison to conventional single-threaded
execution on a state-ofthe-art superscalar microarchitecture with
comparable cost, SHREC reduces the average performance penalty to
within 4% on integer and 15% on floating-point SPEC2K benchmarks
by sharing resources more efficiently between the redundant threads.
Jared Smolens is a third year PhD student in the Computer Architecture
Laboratory at Carnegie Mellon, where he is advised by Prof. James
Hoe. His time is primarily devoted to the TRUSS project. His research
interests include multiprocessor and microprocessor architecture,
fault tolerance, and performance modeling.