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TurboSmarts: They've gone to plaid!

Tuesday September 7, 2004
Hamerschlag Hall 1112
4:00 pm

Thomas Wenisch & Roland Wunderlich
Carnegie Mellon University

Prior work here at Carnegie Mellon, titled Smarts, proposed accelerating microarchitecture simulation by extracting a small but representative fraction of a benchmark's execution trace through statistical sampling. To minimize error and increase confidence in performance estimates, Smarts advocates detailed microarchitecture simulation of a large number (e.g., 10,000) of brief (e.g., 1000-instruction) execution windows. Although this approach requires only minutes of detailed simulation, warming requirements increase total turnaround times to hours.

In this talk, we review our prior work on Smarts (last presented to CALCM on 5/8/2003) and introduce TurboSmarts, a new framework that stores warmed state in a library of reusable checkpoints. The fundamental insight enabling TurboSmarts is that only a tiny fraction of warmed state is necessary to measure brief execution windows. By identifying and storing a minimal subset of model state in checkpoints, TurboSmarts can replace slow functional warming with rapid loading of checkpoints, reducing simulation runtime to minutes. We demonstrate that TurboSmarts can accurately estimate the performance of an 8-way out-of-order superscalar processor running SPEC CPU2000 in 91 seconds per benchmark on average with a 12 GB checkpoint library for the entire benchmark suite.

Thomas Wenisch is a fourth year PhD student in computer architecture, working with Prof. Babak Falsafi. Tom makes databases run faster on multiprocessors.

Roland Wunderlich is a fourth year PhD student in computer architecture, working with Prof. James Hoe. Roland makes digital signal processing run faster on VLIW.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science