April 16, 2002 Tuesday
Hamerschlag Hall 1112
Department of ECE
Department of ECE
Microarchitecture researchers today are wasting time by over-simulating
their designs, and are also not getting accurate performance
results for their efforts. Computer architects want to measure
the performance of their designs using benchmarks like SPEC
2000, but simulators such as SimpleScalar have huge slowdowns
of up to 10,000 times slower versus real CPU's. Running individual
SPEC 2000 benchmarks to completion to obtain accurate performance
numbers can take multiple weeks on the fastest computers.
As a result, researchers normally run less that 0.1% of these
programs due to time and resource constraints. We have determined
that this practice often produces results wildly inconsistent
with results from a complete simulation.
To attack the low speed of simulation, we looked at the nature
of the instruction streams in these benchmarks, and derived
the minimum fractions that need to be sampled to obtain accurate
results. We also determined analytical models for the rate
of simulation of various levels of architectural complexity.
Merging these results with a periodic fast forwarding simulation
approach, we propose a technique which provides superior results
while also accelerating simulation by up to three orders of
Wunderlich is a first year graduate student in the Electrical
and Computer Engineering department at Carnegie Mellon University.
His advisor is Prof. James Hoe. His research is
focused on microprocessor architecture and high-level prototyping
using operation centric hardware design languages. Somehow, Rutgers
University handed over a B.S. degree in Computer Engineering to him
Tom Wenisch is a first year PhD student in ECE under Babak Falsafi.
Tom's interests include instruction/thread level parallelism, memory
system design, and performance evaluation methodology. Nowadays, Tom
spends most of his time hacking an out-of-order processor simulator
around Virtutech's Simics simulation infrastructure.