Performance Microarchitectural Fault Tolerance
Tuesday March 11, 2003
Hamerschlag Hall 1112
Carnegie Mellon University
Designers will soon face microarchitectural challenges keeping processors
resistant to transient faults from cosmic rays and alpha particles. Previous
work has shown, with a 30% average IPC loss, the feasibility of modifying
a superscalar datapath to achieve transient fault detection and recovery.
I will present work in progress showing that program bandwidth requirements
vary with time, creating regions where redundant threads simultaneously
place high bandwidth demands on the processor. Replication and execution
of misspeculated instructions also waste bandwidth and can increase branch
resolution latency. By prioritizing one thread and interleaving opposing
regions of each thread with a dynamically-allocated slack buffer, dispatch
and issue bandwidth demands of the other may be deferred to later, uncontended
cycles. Preliminary results of this work will be presented.
Jared Smolens is a first year Ph.D. student in the Computer Architecture
Laboratory at Carnegie Mellon University, where he is advised by Dr. James
Hoe. His research interests include multiprocessor and microprocessor
architecture, fault tolerance, and performance modeling.