Table of Contents

CARM: Cache-aware Roofline model for Multicores

Tuesday September 27th, 2016
Location: Panther Hollow Conference Room, CIC - 4th Floor
Time: 4:30PM

Leonel Sousa (IST Portugal)


As computer architectures evolve towards more complex mix of multiple cores specialized for different domains, deciding what optimizations provide the best tradeoff between performance and energy efficiency is becoming a prominent issue. To support this decision process, we propose a set of fundamental models (CARM) to characterize the attainable upper-bounds for performance, power and energy efficiency of modern multi-cores. The proposed approach evaluates how key micro-architectural aspects, such as accessing different functional units or different levels of the memory hierarchy, may affect the attainable performance and power consumption of the processor. The effectiveness of the proposed models is evidenced by experimentally assessing the behavior of applications from SPEC CPU 2006, PARSEC, SPLASH and Intel MKL suites. Finally, we present a proof-of-concept example to illustrate how the proposed models can be applied to optimize parallel applications, and we will show how the Intel Advisor tools integrate CARM.


Leonel Sousa received a Ph.D. degree in Electrical and Computer Engineering from the Instituto Superior Tecnico (IST), Universidade de Lisboa (UL), Lisbon, Portugal, in 1996, where he is currently Full Professor. He is also a Senior Researcher with the R&D Instituto de Engenharia de Sistemas e Computadores (INESC-ID). His research interests include VLSI architectures, parallel computing and computer arithmetic. He has contributed to more than 200 papers in journals and international conferences, for which he got several awards. He has been involved in the organization of international conferences, he has edited four special issues of international journals, and he is currently Associate Editor of the IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Access, IET Electronics Letters and Springer JRTIP, and Editor-in-Chief of the Eurasip JES. He is Fellow of the IET, Distinguished Scientist of ACM and Senior Member of IEEE.

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