Tuesday May 2, 2017
Location: CIC Panther Hollow Room
Gabriel H. Loh (AMD Research)
The need for ever more powerful supercomputers does not appear to be slowing down, but the challenges to push computing to exaFLOP levels and beyond are becoming increasingly difficult. Given government targets for computing throughput, memory capacity, memory bandwidth, power efficiency, reliability, and cost, in this talk I will present one possible vision for a processor architecture that can be used to construct exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is a computational building block for an exascale supercomputer. The ENA consists of an Exascale Heterogeneous Processor (EHP) coupled with an advanced memory system. The EHP provides a high-performance accelerated processing unit (CPU+GPU), in-package high-bandwidth 3D memory, and aggressive use of die-stacking and chiplet technologies to meet the requirements for exascale computing in a balanced manner. In addition to detailing our approach, I will also discuss some of the remaining open research challenges for the community.
Gabriel H. Loh is a Fellow Design Engineer in AMD Research, the research and advanced development lab for Advanced Micro Devices, Inc. Gabe received his Ph.D. and M.S. in computer science from Yale University, respectively, and his B.Eng. in electrical engineering from the Cooper Union. Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. He is an IEEE Fellow and distinguished scientist of the ACM, (co-)inventor on over eighty US patent applications and twenty-seven granted patents, and a recipient of the U.S. National Science Foundation Young Faculty CAREER Award. His interests include computer architecture, processor microarchitecture, memory systems, emerging technologies, 3D die stacking.