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FPGA Acceleration for Convolutional Neural Networks

Monday March 27, 2017
Location: CIC Panther Hollow Room
Time: 4:30PM

Peter Milder (Stony Brook University)


Deep learning and convolutional neural networks (CNNs) are revolutionizing machine learning applications such as computer vision, fraud detection, and natural language processing. At tasks such as visual object detection and classification, deep CNN-based systems are consistently improving on the state of the art. However, these algorithmic breakthroughs have come at a steep computational cost, necessitating the use of new hardware to enable this rapid growth to continue. This talk will describe recent progress on using field programmable gate arrays (FPGAs) to accelerate deep learning algorithms, focusing on new structures that exhibit better utilization of FPGA resources, and on new algorithms that greatly reduce the off-chip data bandwidth required by the accelerator.


Peter Milder is an Assistant Professor in the Department of Electrical and Computer Engineering at Stony Brook University. His research focuses on hardware acceleration and FPGAs, especially for machine learning and signal processing applications. Peter received the BS, MS, and PhD degrees in Electrical and Computer Engineering from Carnegie Mellon University in 2004, 2005, and 2010, respectively.

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