Tuesday Oct. 12, 2010
Location: Hamerschlag Hall D-210
Carnegie Mellon University
In recent years, chip multiprocessors (CMPs) have continued to grow in number of cores. As more cores are placed on one chip, the communication between them requires higher bandwidth; thus, traditional busses and other central structures will be replaced by on-chip networks. Many recent papers in computer architecture have evaluated on-chip network architectures for the purpose of building large CMPs. Curiously, so far these networks have not attracted significant attention from the networking community. In this talk, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting core differences between NoCs and traditional networks. As an initial case study, we examine network congestion in bufferless NoCs. We show that congestion manifests itself differently in a NoC than in a traditional network, and requires application-level awareness in the network to make proper throttling decisions. From this, we develop a centrally coordinated congestion control mechanism, at a low complexity cost, which improves overall system performance by up to 28%. It is our hope that the unique and interesting challenges of on-chip network design can be met by novel and effective solutions from the networking community.
George Nychis is a graduate student at Carnegie Mellon University pursuing his Ph.D. in Electrical and Computer Engineering, advised by Peter Steenkiste and Srinivasan Seshan. He received his M.S. from the Information Networking Institute at Carnegie Mellon University, and his B.S. in Computer Science from the University of Pittsburgh. George's research interests are in the field of networking with a focus on wireless networks, software-defined radios, and dynamic spectrum access. However, he has a strong belief that NoCs present a novel networking architecture with numerous challenges that can benefit from focus in the networking community.
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