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Hardware Transactional Memory in the Wild

Konrad Lai (Intel)

Friday, Oct. 3rd, 2:00PM-3:00PM
CIC Panther Hollow


Intel has recently introduced Intel Transactional Synchronization Extensions (Intel TSX) in the Intel 4th Generation Core Processors. With Intel TSX, a processor can dynamically determine whether threads need to serialize through lock-protected critical sections. We evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads, and demonstrate that applying Intel TSX to these workloads can provide significant performance improvements. On a set of real-world HPC workloads, applying Intel TSX provides an average speedup of 1.41. When applied to a parallel user-level TCP/IP stack, Intel TSX provides 1.31 average bandwidth improvement on network intensive applications. We also demonstrate the ease with which we were able to apply Intel TSX to the various workloads.


Konrad Lai received the BSE from Princeton University and MSCE from Carnegie Mellon University. He is has recently retired as a Senior Principal Research Scientist in the Microprocessor Technology Laboratories, Intel Corporation. He was with Intel for over 30 years, working on object oriented architecture, microprocessor, multiprocessor system, memory technology, and system architecture.

His current research interests include advanced microarchitecture, FPGA prototype, and hardware/software support for multi/many-core architecture.