(click to enlarge)
On-chip communication via the Network-on-Chip (NoC) approach
and its practical implementation using a Virtex2-Pro FPGA from
Xilinx. Future technologies will make possible the actual implementation
of multiple Voltage/Frequency Islands (VFIs) as shown on the left
hand side of this figure. Such advanced features will enable NoC
designs consisting of multiple VFIs to cope with power consumption,
clock distribution, and parameter variation issues in future multiprocessor
systems-on-chip.
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Systems
This
area focuses on tools and design methodologies for modeling, analysis,
and optimization of critical design constraints (performance, power,
reliability, etc.) at the system and architecture level. With the increased
need for addressing challenges due to more on-chip complexity, communication
and power costs, and design variability, new design aids are essential
very early in the design process. Research in this area targets scalable
performance, power and reliability modeling, and associated novel design
paradigms for dealing with on-chip communication, power management, and
variability-aware design.
Area Leader
Researchers
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