Shawn Blanton, PhD

Research Area

• Manufacturing, Systems

Representative Publications

• R. D. Blanton, K. N. Dwarakanath and R. Desineni, “Fault Modeling using Fault Tuples,” IEEE Transactions on CAD, vol. 25, no. 11, pp. 2450-2464, Nov. 2006.
• S. Biswas and R. D. Blanton, “Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data,” Design IEEE VLSI Test Symposium, May 2008.
• J. G. Brown, B. Taylor, R. D. Blanton and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries,” Design, Test and Automation in Europe, March 2008.
• Y-T. Lin, O. Poku, N. K. Bhatti and R. D. Blanton, “Physically-Aware N-Detect Test Pattern Selection,” Design, Test and Automation in Europe, March 2008.
• R. Desineni, O. Poku and R. D. Blanton, “A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior,” IEEE International Test Conference, Oct. 2006.