Research

Our work in the Advanced Chip Testing Laboratory (ACTL) is centered on extracting valuable information from the data generated from chip testing. The plot in the figure to the right shows how test yield fluctuates for two real chips fabricated in the same facility. There are several important observations drawn from the plot:

• Yield is not 100% and can improve and degrade over time.
• Yield fluctuations are not uniform, implying that each chip has its own unique susceptibilities to perturbations in the fabrication process.
• Since test is not perfect, the number of good (bad) chips that are falsely rejected (accepted) will fluctuate with yield.

Active projects in ACTL are centered on analyzing test data to ensure reliable chip operation, improve chip design and fabrication to maximize yield, and customize test to prevent bad chips from escaping to the next level of integration. Specific research themes within ACTL include:

Chip Diagnosis

The traditional objective of diagnosis is to locate the site of failure within a non-working chip. In our work, the objective is instead to completely characterize the failure, that is, (i) locate it, (ii) describe its impact on the chip’s functionality and performance, and (iii) understand its likelihood of re-occurrence in the chips yet to be fabricated. The last objective can only be ascertained by diagnosing an entire population of failing chips (known as volume diagnosis).  Representative publications from this research include:

• X. Yu and R. D. Blanton, “Integrated Circuit Diagnosis of Circuits with Multiple Defects of Arbitrary Characteristics”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 977 - 987, June 2010.
• J. E. Nelson, W. Tam, and R. D. Blanton, “Automatic Classification of Bridge Defects,” International Test Conference, Oct. 2010.
  
• R. Desineni and R. D. Blanton, “Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction,” IEEE VLSI Test Symposium, pp. 366- 373, May 2005.

Test Data Analysis

We are using various statistical and machine-learning techniques to extract valuable information from test data. Specifically, characteristics of the fabrication process, the design, and the test process itself can be obtained from statistically analyzing test data. Results of this test-data analysis are being used to improve chip design, fabrication and test.  Representative publications from this research include:

• X. Yu and R. D. Blanton, “Statistical Defect-Detection Analysis of Test Sets using Readily-Available Tester Data,” International Conference on Computer-Aided Design, Nov. 2011.
• W. C. Tam and R. D. Blanton “To DFM or Not to DFM,” Design Automation Conference, June 2011.

Chip Testing

We are developing several new methodologies for improving the effectiveness of test to detect failing chips. Our approaches utilize non-traditional input sources that include the physical description of the design (i.e., the layout) and diagnostic results. This information along with new fault modeling techniques enables a customized approach for each chip and its corresponding fabrication process. Representative publications from this research include:

• Y.-T Lin and R. D. Blanton, “METER: Measuring Test Effectiveness Regionally,” IEEE Transactions on CAD, Vol. 30, No. 7, pp. 1058-1071, July 2011.
• X. Yu, Y.-T. Lin, W. C. Tam, O. Poku and R. D. Blanton, “Controlling DPPM through Volume Diagnosis,” IEEE VLSI Test Symposium, May 2009.
  

Virtual Populations

Our projects use real test data from hundreds of thousands of failing chips. Although the use of real data shows the viability of our methodologies on modern-day chips, it is difficult to verify accuracy since it is extremely expensive to physically uncover the source of failure within a chip. To overcome this challenge, we create virtual populations of failing chips with known characteristics using layout modification, extraction, and circuit-level simulation. Representative publications from this research include:

• W. C. Tam and R. D. Blanton “SLIDER: A Fast and Accurate Defect Simulation Framework,” IEEE VLSI Test Symposium, May 2011.
• Vogels et. al, “Benchmarking Diagnosis Algorithms with a Diverse Set of IC Deformations,” IEEE International Test Conference, pp. 508-517, Oct. 2004.