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Publications


Patents

  1. United States Provisional Patent Application No. 61/397,605, W. Tam and R. D. Blanton “Systematic Defect Identification and Elimination through Layout Snippet Clustering,” Filed June 14, 2010.

  2. United States Patent Application No. 11/651,782, R. D. Blanton, R. Desineni, and W. Maly, “Method and System for Logic-Level Diagnosis for Arbitrary Defects in VLSI Circuits,” Issued Aug. 3, 2010.

  3. United States Patent Application No. 12/473,749, X. Li, R. Rutenbar and R. D. Blanton “Virtual Probe for Low-Cost Testing and Characterization for Integrated Circuits,” Filed May 2009.

  4. United States Patent No. 7,340,956, N. Deb and R. D. Blanton, “Built-in Self Test for MEMS,” Issued March 11, 2008.

  5. United States Patent No. 7,325,180, L. Pileggi, P. Yue, T. Vogels, and R. D. Blanton, “System and Method to Test Integrated Circuits on a Wafer,” Issued Jan. 29, 2008.

  6. United States Patent No. 7,152,474, N. Deb and R. D. Blanton, “Built-in Self Test for MEMS,” Issued Dec. 6, 2006.

  7. United States Patent No. 6,836,856, R. D. Blanton “Method for Characterizing, Generating Test Sequences for, and/or Stimulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Programs and Products,” Issued Dec. 28, 2004.