Journal Papers   |   Conference Papers   |   Other Papers   |   Patents

Publications


Other Papers

  1. X. Li, R. Rutenbar, and R. D. Blanton, “Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Feb. 2009.

  2. Y. Lin, O. Poku, N. Bhatti, and R. D. Blanton, “Physically-Aware N-Detect Test Pattern Selection,” SRC TECHCON 2007, Publication P019825, Sept. 2007.

  3. J. E. Nelson, W. Maly, and R. D. Blanton, “Diagnosis-Enhanced Extraction of Defect Density and Size Distributions from Digital Logic ICs,” SRC TECHCON 2007, Publication P019906, Sept. 2007.

  4. J. Brown and R. D. Blanton, “Diagnosis Automated Testability Enhancements for Logic Brick Libraries,” SRC TECHCON 2007: Invited Session - Focus Center Research Program, Paper FCRP.6, Sept. 2007.

  5. T. Zanon, J. Nelson, J. Brown, R. Desineni, N. Patil, W. Maly and R. D. Blanton, “Extraction of Defect Density Size Distributions from Product Test Results,” SRC TECHCON 2005, Oct. 2005.

  6. J. E. Nelson and R. D. Blanton, “Multiple-Detect Test Generation Based on Physical Neighborhoods,” SRC TECHCON 2005, Oct. 2005.

  7. R. D. Blanton and S. Mitra, “Tutorial: Testing Nanometer Digital Integrated Circuits: Myths, Reality and the Road Ahead,” International Conference on VLSI Design, pp. 8-9, Jan 2005.

  8. R. Desineni, T. J. Vogels, K. N. Dwarakanath, T. Zanon, R. D. Blanton and W. Maly, “A Multi-Stage Approach to Fault Identification Using Fault Tuples,” International Symposium for Testing and Failure Analysis, pp. 496-505, Nov. 2003.

  9. R. Kundu and R. D. Blanton, “Test Generation for Noise-Induced Switch Failures in Domino Logic Circuits,” SRC TECHCON 2003, Aug. 2003.

  10. R. Desineni, K. N. Dwarakanath and R. D. Blanton, “Test Analysis Using Fault Tuples,” SRC TECHCON 2000, Publication P000697, Sept. 2000.

  11. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Buffer-Oriented Microarchitecture Validation (BMV),” SRC TECHCON 2000, Publication P000713, Sept. 2000.

  12. R. Kundu and R. D. Blanton, “Identification of Crosstalk Switch Faults in Domino CMOS Circuits,” SRC TECHCON 2000, Publication P000704, Sept. 2000.

  13. S. Mir, H. Kerkhoff, R.D. Blanton, H. Bederr and H. Klim, “SoCs with MEMS? Can we include MEMS in the SoCs Design and Test Flow?” IEEE VLSI Test Symposium, p. 449, April 2002.

  14. R. D. Blanton, “The Challenge of MEMS Testing,” IEEE International Test Conference, p. 1133, Oct. 2000.

  15. R. D. Blanton and B. Courtois, “Guest Editor’s Introduction: MEMS Design and Test,” IEEE Design & Test of Computers, vol. 16,  no. 4,  pp. 16-17,  Oct-Dec,  1999.

  16. G. K. Fedder and R. D. Blanton, “Characterization and Reliability of CMOS Microstructures,” SPIE Conference on MEMS Reliability for Critical Applications, pp. 132–139, Sept. 1999.

  17. T. Jiang, C. Kellen and R. D. Blanton, “Inductive Fault Analysis of a Microresonator,” International Conference on Modeling and Simulation of Microsystems Semiconductors, Sensors and Actuators, pp. 498– 501, April 1999.

  18. R. D. Blanton, G. K. Fedder and T. Mukherjee, “Hierarchical Design & Test of MEMS,” Microsystems Technology News, no. 1, pp. 28–31, April 1998.

  19. N. Deb, S. Iyer, T. Mukherjee and R. D. Blanton, “MEMS Resonator Synthesis for Testability,” Symposium on Design Test and Microfabrication of MEMS/MOEMS, pp. 58-69, March 1999.

  20. Kolpekwar, C. Kellen and R. D. Blanton, “Fault Model Generation for MEMS,” International Conference on Modeling and Simulation of Microsystems, Semiconductors, Sensors and Actuators, pp. 111– 116, April 1998.

  21. R. D. Blanton and T. Jiang, “Inductive Fault Analysis of a MEMS Resonator,” MEMS/MST and Their Perspective in Electronic Systems Workshop, March 2005.

  22. R. D. Blanton, K. Dwarakanath and A. Shah, “Realistic N-Detect Analysis,” IEEE 12th North Atlantic Test Workshop, May 2003.

  23. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Relating Buffer-Oriented Microarchitecture Validation to High-Level Pipeline Functionality,” IEEE International High Level Design Validation and Test Workshop, pp. 3–8, Nov. 2001.

  24. V. Chickermane, K. Dwarakanath and R. D. Blanton, “Synthesis of HDL Structures for Random Pattern Testability,” International Test Synthesis Workshop, March 2001.

  25. R. D. Blanton, “Failure Analysis Using Fault Tuples,” 2nd Annual Latin American Test Workshop, pp. 253–257, Feb. 2001.

  26. N. Utamaphethai, R. D. Blanton, J. P. Shen, P. Bose, “Effectiveness Evaluation of the Buffer-Oriented Microarchitecture Validation Methodology,” International Workshop on Microprocessor Test and Verification, Sept. 1999.

  27. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Validation of Speculative and Out-of-Order Execution Microarchitecture,” International Workshop on Microprocessor Test and Verification, Oct. 1998.

  28. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Superscalar Processor Validation at the Microarchitecture Level,” IEEE International High Level Design Validation and Test Workshop, pp. 202–209, Nov. 1997.