Sounil Biswas



Contact Information

Affiliation                :   Center for Silicon System Implementation [CSSI]

Department               :  Electrical and Computer Engineering

School                       :  Carnegie Mellon University

Address                     :  5000 Forbes Avenue,
                                     Carnegie Mellon University,
                                     Department of Electrical and Computer Engineering,
                                     HH# 2131,
                                     Pittsburgh, PA 15213.

Phone No.                 :  412-268-5234

Fax                            :  412-268-1374

Email                        :   sbiswas@andrew.cmu.edu

Personal Details

Date of Birth            :  May 25th, 1979
Place of Birth           :  Calcutta, India
Citizenship               :  Indian
Present Residence    :  Pittsburgh, USA

Academic Background

I have been born and brought up in Calcutta, India. I have undergone basic schooling there. Then I went for undergraduate college to Indian Institute of Technology, Kanpur [IITK]. I had undergraduate schooling from July 1998 till May 2002 in the department of  Electrical Engineering. I completed undergraduate schooling with 3rd position in the department and a cumulative performance index of 9.5 (out of 10.0). During my undergraduate studies I have received several academic excellency awards for outstanding academic performance during different academic years including best student performace award in the department for the academic year of 2000-2001. During the academic year of 2001-2002 I also completed Bachelor's research under the supervision of  Prof. Baquer Mazhari to publish a paper at the  16th International Conference on VLSI Design and Second International Conference on Embedded Systems Design (see publication 1).
    After finishing undergraduate studies I joined the department of Electrical Engineering at  Carnegie Mellon University in Pittsburgh, Pennsylvania (USA) in persuance of the degree of Master of Science (M.S.) extending to the degree of Doctor of Philosopsy (Ph.D.) with full scholarship. I completed my M.S. degree in May 2004. Presently I am a doctoral candidate at Carnegie Mellon University under  Prof. R. D. (Shawn) Blanton.

Research Interest

1. Digital test generation and fault simulation.
2. Delay Test
3. Analog and mixed signal test.
4. Test cost reduction and test ecomonics.

Publications

1. S. Biswas and R. D. Blanton, “Statistical Test Compaction using Binary Decision Trees,” IEEE Design & Test of Computers: Special Issue on Process Variation and Stochastic Design and Test, vol. 23, no. 6, pp. 452 – 462 , Jun. 2006.
2. S. Biswas, P. Li, R. D. Blanton, L. T. Pileggi, "Specification Test Compaction for Analog Circuits and MEMS," Proc. of Design, Automation and Test Conf. in Europe,  pp. 164-169, Mar. 2005.
3. S. Biswas, K.N. Dwarakanath and R. D. (Shawn) Blanton, "Generalized Sensitization using Fault Tuples", Proc. of VLSI Test Symposium, pp. 297-303, Apr. 2004.
4. S. Biswas, “Generalized Sensitization Using Fault Tuples,” Master’s Thesis, Carnegie Mellon University, Apr. 2004.
5. S. Biswas and B. Mazhari, "A Path Sensitization Technique for Testing of Switched Capacitor Circuits", Proc. of the 16th Intl. Conf. on VLSI Design, pp. 30-35, Jan. 2003.
   
   
   

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Last modified: Tue Dec 09 15:18:15 EDT 2003