Roland Wunderlich
| e_mail | rol...@wunderlich.com / rol...@cmu.edu | |
| office | Hamerschlag Hall A300 | |
| university | Carnegie Mellon University | |
| department | Electrical and Computer Engineering | |
| affiliations | Computer Architecture Lab at Carnegie Mellon Spiral Project | |
| advisor | Prof. James Hoe | |
| doctoral research | Performance counter super-resolution
Hardware performance counters are invaluable tools to gain visibility to the internal operations of modern microprocessors during performance debugging and tuning. Unfortunately, attempting to extract measurements from hardware performance counters at too fine a granularity can perturb execution behavior and introduce context-sensitive observation effects; thus measurement intervals can be no smaller than milliseconds, i.e., tens of millions of instructions in modern CPUs. We are developing a super-resolution approach where low-resolution performance counter measurements, taken redundantly over multiple iterations of a program, are combined to reconstruct a high-resolution dynamic counter profile over a programs execution trace. |
|
| publications |
Our publications cover statistical sampling of microarchitecture simulation, FPGA prototyping of microarchitectures, and optimized matrix-matrix multiplication on embedded microarchitectures. The comprehesive list of my publications is below, but some of the papers and technical reports have been superseded by later and more comprehensive works.
Uni-processor simulation sampling: TOMACS 2006, ISPASS 2006 FPGA prototyping: ICCD 2004 Matrix-matrix multiplication: HPEC 2005 |
|
| peer-reviewed publications |
Journal article
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, J. C. Hoe, "Statistical Sampling of Microarchitecture Simulation," ACM Transactions on Modeling and Computer Simulation (TOMACS), vol. 16, no. 3, July 2006. Magazine publication T. F. Wenisch, R. E. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, J. C. Hoe, "SimFlex: Statistical Sampling of Computer System Simulation," IEEE Micro Special Issue on Computer Architecture Simulation and Modeling, vol. 26, no. 4, July/August 2006. Conference publications T. F. Wenisch, R. E. Wunderlich, B. Falsafi, J. C. Hoe, "Simulation Sampling with Live-Points," Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2006. R. E. Wunderlich and J. C. Hoe, "In-System FPGA Prototyping of an Itanium Microarchitecture," Proceedings of the 22nd International Conference on Computer Design (ICCD), October 2004. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, J. C. Hoe, "Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling," Proceedings of the 30th International Symposium on Computer Architecture (ISCA), June 2003. (superseded by the 2006 TOMACS journal article) Workshop publication R. E. Wunderlich, T. F. Wenisch, B. Falsafi, J. C. Hoe, "An Evaluation of Stratified Sampling of Microarchitecture Simulations," Third Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD at ISCA-31), June 2004. Extended abstracts with poster R. E. Wunderlich, M. Püschel, and J. C. Hoe, "Accelerating Blocked Matrix-Matrix Multiplication using a Software-Managed Memory Hierarchy with DMA," Ninth Annual Workshop on High Performance Embedded Computing (HPEC), September 2005. (poster materials) T. F. Wenisch, R. E. Wunderlich, B. Falsafi, J. C. Hoe, "TurboSmarts: Accurate Microarchitecture Simulation Sampling in Minutes," Proceedings of the International Conference on Measurement & Modeling of Computer Systems (SIGMETRICS), June 2005. R. E. Wunderlich and J. C. Hoe, "In-System FPGA Prototyping of an Itanium Microarchitecture," Proceedings of the 12th International Symposium on Field Programmable Gate Arrays (FPGA), February 2004. |
|
| other publications |
Invited paper
N. Hardavellas, S. Somogyi, T. F. Wenisch, R. E. Wunderlich, S. Chen, J. Kim, B. Falsafi, J. C. Hoe, and A. G. Nowatzyk, "SimFlex: A Fast, Accurate, Flexible Full-System Simulation Framework for Performance Evaluation of Server Architecture," ACM SIGMETRICS Performance Evaluation Review, March 2004. Technical reports T. F. Wenisch, R. E. Wunderlich, B. Falsafi, J. C. Hoe, "TurboSmarts: Accurate Microarchitecture Simulation Sampling in Minutes," Technical Report 2004-3, Computer Architecture Laboratory at Carnegie Mellon University (CALCM), November 2004. (superseded by the 2006 ICCD publication) T. F. Wenisch, R. E. Wunderlich, B. Falsafi, J. C. Hoe, "Applying Smarts to SPEC CPU2000," Technical Report 2003-1, Computer Architecture Laboratory at Carnegie Mellon University (CALCM), June 2003. (superseded by the 2006 TOMACS journal article) |
|
| external academic talks | Tutorials & seminars
T. F. Wenisch, R. E. Wunderlich, "SimFlex: Fast, Accurate and Flexible Simulation of Computer Systems," Tutorial at the 33rd International Symposium on Computer Architecture (ISCA), June 2006. T. F. Wenisch, R. E. Wunderlich, "SimFlex: Fast, Accurate and Flexible Simulation of Computer Systems," Tutorial at the 38th International Symposium on Microarchitecture (MICRO), November 2005. (superseded by the 2006 ISCA tutorial) R. E. Wunderlich, T. F. Wenisch, "Smarts & TurboSmarts," Seminar at Princeton University, August 2004. (superseded by the 2006 ISCA tutorial) R. E. Wunderlich, "Modeling and FPGA Prototyping of an Itanium Architecture," Seminars at Intel Corporation (μAL & SCL), August 2003. R. E. Wunderlich, "Smarts: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling," Seminar at Intel Corporation (μAL), July 2003. (superseded by the 2006 ISCA tutorial) |
|