Patents

1. U.S. Patent No. 7,350,164 – Optimization and Design Method For Configurable Analog circuits And Devices – Xu, Pileggi and Boyd, March 2008.
2. U.S. Patent No. 7,325,180 – System and Method to Test Integrated Circuits on a Wafer - Pileggi, Yue, Blanton and Vogels, January 2008.
3. U.S. Patent No. 7,278,118 - “Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features” – Pileggi, Strojwas and Lanza, October 2, 2007.
4. U.S. Patent No. 7,096,174 - "Systems, Method and Computer Program Products for Creating Hierarchical Equivalent Circuit Models" - Beattie and Pileggi, August 22, 2006.
5. U.S. Patent No. 6,961,916 - "Placement method for integrated circuit design using topo-clustering" - Sarrafzadeh, Pileggi, et al, November 1, 2005.
6. U.S. Patent No. 6,820,245 - " Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized models," - Beattie and Pileggi, November 16, 2004.
7. U.S. Patent No. 6,775,808- "Method and Apparatus for Generating Sign-Off Prototypes for the Design and Fabrication of Integrated Circuits" - Raje, Pileggi, et al, August 10, 2004.
8. U.S. Patent No. 6,651,232 - "Method and System for Progressive Clock Tree or Mesh Construction Concurrently with Physical Design" - Pileggi et al, November, 2003.
9. U.S. Patent No. 6,633,182 - "Programmable Gate Array Based on Configurable Metal Interconnect Vias" - Pileggi and Schmit, June 2003.
10. U.S. Patent No. 6,449,756 - "A Method for Accurate and Efficient Updates of Timing Information During Logic Synthesis, Placement and Routing for Integrated Circuits" - Malik, Pileggi, et al, Sept 2002.
11. U.S. Patent No. 6,442,743 - "Placement Method for Integrated Circuit Design using TopoClustering" - Sarrafzadeh, Pileggi, et al, Aug 2002.
12. U.S. Patent No. 6,385,760 - "System and Method for Concurrent Placement of Gates and Associated Wiring" - Pileggi, Sarrafzadeh, et al, May 2002.
13. U.S. Patent No. 6,367,051 - "System and Method for Concurrent Buffer Insertion and Placement of Logic Gates" - Pileggi, Sarrafzadeh, et al, April 2002.
14. U.S. Patent No. 6,286,128 - "Method for Design Optimization using Logic and Physical Information" - Pileggi et al, September 2001.
15. U.S. Patent No. 6,192,508 - "Method for Logic Optimization for Improving Timing and Congestion During Placement in Integrated Circuit Design" - Malik, Pileggi et al, Feb. 2001.
16. U.S. Patent No. 5,379,231 - "Method and Apparatus for Simulating a Microelectronic Interconnect Circuit" - Pillage, Ratzlaff and Gopal, January 1995.
17. U.S. Patent No. 5,023,822 - "Pulse Ratio System" - Schlotterer, Johnston, Rusnak, Pillage, and Byrd.
18. U.S. Patent No. 4,683,989 - "Elevator Communications Controller" - Pillage and Anderson, Westinghouse R&D.