Refereed Archival Journal Publications    |    Refereed Conference Publications    |    Patents

 

Refereed Archival Journal Publications

  1. Xin Li, Yaping Zhan and Lawrence Pileggi, Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits, To appear in IEEE Transactions on Computer-Aided Design.
  2. Xin Li, Jiayong Le, Lawrence Pileggi, "Statistical Performance Modeling and Optimization", Foundations and Trends in Electronic Design Automation: Vol. 1: No 4, pp 331-480, 2007.
  3. Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” submitted to Proceedings of The IEEE (PTI).
  4. Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., "Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity", Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03) (accepted).
  5. Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence Pileggi, "Asymptotic probability extraction for non-Normal performance distributions," IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
  6. Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence Pilegg, "Robust analog/RF circuit design with projection-based performance modeling," IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
  7. P. Li, L. Pileggi, M. Ashegi, R. Chandra, Efficient Full-Chip Thermal Modeling and Analysis, Accepted for publication in IEEE Transactions on CAD.
  8. Yang Xu, Larry Pileggi, Stephan Boyd, ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction, Submitted to IEEE Transactions on CAD.
  9. P. Li and L. T. Pileggi, Compact Reduced-Order Modeling of Weakly Nonlinear Analog and RF Circuits, IEEE Transactions on Computer-Aided Design, Vol. 23, No. 2, pp. 184-203, February 2005.
  10. Y. Xu, C. Boone and L. Pileggi, Metal-mask configurable RF Front-end Circuits, IEEE Journal of Solid State Circuits, Volume: 39, Issue: 8, pp. 1347-1351, Aug. 2004.
  11. H. Zheng, B. Krauter and L.T. Pileggi, Electrical Modeling of Integrated-Package Power/Ground Distributions, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
  12. M. Beattie and L.T. Pileggi, Parasitic Extraction with Multipole Refinement, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
  13. P. Li and L. T. Pileggi, Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
  14. D. Pandini, L. T. Pileggi and A.J. Strojwas, Global and Local Congestion Optimization in Technology Mapping, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.
  15. R. Arunachalam, R. D. Blanton, L. T. Pileggi, "Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation," VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, 2002.
  16. E. Acar, F. Dartu and L. T. Pileggi, TETA: Transistor level Waveform Evaluation for Timing Analysis, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
  17. M. Beattie and L.T. Pileggi, On-Chip Induction Modeling: Basics and Advanced Methods, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
  18. P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, Overcoming Wireload Model Uncertainty for Physical Design, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January, 2002.
  19. R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
  20. Y. Liu, L. T. Pileggi and A.J. Strojwas, ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits, IEEE Transactions on Circuits and Systems, April 2001.
  21. M. Beattie, B. Krauter, L. Alatan and L. Pileggi, Equipotential Shells for Efficient Inductance Extraction, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
  22. M. Celik and L. T. Pileggi, Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
  23. M. Beattie and L. T. Pileggi, Bounds for BEM Capacitance Extraction, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
  24. Rohini Gupta, John Willis and L.T. Pileggi, Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
  25. A. Odabasioglu, M. Celik and L. T. Pileggi, PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
  26. R. Kay and L. Pileggi, EWA: Efficient Wire Sizing Algorithm, IEEE Transactions on Computer-Aided Design, January, 1998.
  27. M. Celik and L. T. Pileggi, Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
  28. N. Menezes, R. Baldick and L.T. Pileggi, A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing, IEEE Transactions on Computer- Aided Design, August 1997.
  29. S. Pullela, N. Menezes and L.T. Pileggi, Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
  30. Rohini Gupta, Byron Krauter and Lawrence Pileggi, Transmission Line Synthesis via Constrained Multivariable Optimization, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
  31. Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, The Elmore Delay as a Bound for RC Trees with Generalized Input Signals, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
  32. Rohini Gupta and Lawrence Pileggi, Modeling Lossy Transmission lines Using the Method of Characteristics, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
  33. S. Pullela, N. Menezes and L.T. Pileggi, Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
  34. Rohini Gupta, John Willis and Lawrence T. Pileggi, Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
  35. F. Dartu, N. Menezes and L.T. Pileggi, Performance Computation for Pre-characterized CMOS Gates with RC Loads, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
  36. Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, Domain Characterization of Transmission Line Models and Analyses, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.
  37. J. Qian, S. Pullela and L.T. Pillage, Modeling the "Effective Capacitance" of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
  38. S.Y. Kim, N. Gopal and L.T. Pillage, Time-Domain Macromodels for VLSI Interconnect Analysis, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
  39. C. Ratzlaff and L.T. Pillage, RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
  40. D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
  41. N. Gopal, A. Balivada and L.T. Pillage, Moment-Matching Approximations for Linear(ized) Circuit Analysis, Semiconductors in IMA Volumes in Mathematics and it’s Applications, F. Odeh, J. Cole, W. M. Coughran, Jr., P. Lloyd, and J. White, editors, Springer-Verlag, pp. 115-130, 1994.
  42. Lawrence T. Pillage, An Early Introduction to Circuit Simulation Techniques, IEEE Transactions on Education, February, 1993.
  43. L.T. Pillage and R.A. Rohrer, Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design (1991 IEEE Best Paper Award), pp. 352-366, April 1990.