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Brian Taylor Optimal Physical Design of Regular Logic Bricks Advisor: Larry Pileggi In recent years the extreme challenges associated with deep subwavelength lithography have prompted research into more lithography-friendly design styles. Researchers in the Regular Fabrics group at Carnegie Mellon University have recently proposed such a design style. In their methodology, the RTL of a design is analyzed and a small set of logic “bricks” (each with a granularity of roughly three to seven NAND2 gates) are derived which efficiently ‘cover’ the design. The brick-level netlist are then mapped onto a regular logic fabric to form a brick. By “logic fabric,” we refer to the physical structures – diffusion, polysilicon, metal, vias, etc. – with which logic circuits are implemented. The regular logic fabric used in this work has the following characteristics: all routing layers (poly and up) are unidirectional; each routing layer has a single, fixed pitch; and the PMOS transistors lie in a single row near the top of the brick, while the NMOS transistors lie in a single row near the bottom of the brick. These restrictions result in the highly regular layout structure illustrated in Figure 1. This work addresses the problem of generating brick layouts for the logic-level netlists extracted from the RTL for a given design. Selected Highlights We attack the brick layout problem by exploiting the structure of the regular fabric to obtain exact combinatorial optimization-based layout algorithms which are either inapplicable to or prohibitively expensive for less regular layout styles. Brick layout generation is done in two steps – transistor placement and routing – and in each step, the regularity of the logic fabric is leveraged by the layout algorithm. In the transistor placement step, the ‘single-row’ diffusion style lends itself to highly effective routability metrics, and to an efficient branch and bound algorithm which is optimal with respect to area and strongly Pareto optimal with respect to the routability metrics. Similarly, the discreteness of the coarse routing grid makes feasible a formulation of the brick routing step as an NP decision problem. In turn, this formulation leads to a SAT-based routing methodology which can make strong guarantees of completeness and optimality that virtually no other routing method can make. We have implemented a prototype brick layout tool that incorporates the exact optimization methods described above. Results on benchmark circuits of various sizes show these methods to be of excellent quality, with layout runtimes measured in seconds.
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Brian Taylor
Figure 1. Regular logic fabric.