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Vyacheslav (Slava) Rovner Regularity-Friendly Circuit Design Advisor: Larry Pileggi The semiconductor industry continues to struggle to achieve sufficient product yields in the most advanced technology nodes. Even though process engineers have been scaling technology in accordance with Moore’s law, they have been unable to control process variations, and thus product yield, to the same extent. The various DFM and DFY methodologies introduced by the industry have increased the burden on the designer through a complex set of the rules specifying the allowed chip geometry. We have taken a radically different approach by creating a regular design fabric to improve yield. The fabric defines legal positions for geometries which have been verified through simulation or silicon. The physical implementation of the circuit is then mapped onto the regular fabric. Based on the limitations of the technology node, two regular fabrics have been developed. The fabrics restrict the poly layer (gates and interconnect) to be uni-directional and occur on a fixed pitch. Likewise, the metal layers are restricted in orientation (metal1 vertical and metal2 horizontal) and pitch. The poly pitch, and thus transistor density, of the Front End Of Line (FEOL) fabric is limited by the FEOL limitations of the process. Specifically, the poly pitch of the FEOL fabric is given by the minimum contacted device pitch and thus prohibits the use of adjacent metal1 tracks. In contrast, the poly pitch of the Back End Of Line (BEOL) fabric is limited by the pitch of metal1, as each transistor uses 3 metal tracks. Selected Highlights The limitations of the technology node will guide the choice of the fabric to be utilized. However, it is important to remember that the overall transistor density, and thus chip area, will be dependent on the selected fabric as well as the circuit that is implemented. From our description of the regular fabrics above, the FEOL fabric is significantly limited in the number of vertical routing tracks. Therefore, a circuit topology requiring a large number of vertical routing tracks will achieve poor transistor density, as devices will have to be spread apart to create additional routing resources. For instance, consider the layout of a commonly used transmission gate based flip-flop as it maps onto the FEOL fabric (Figure 1a). This flipflop topology contains a number of inverters and transmission gates to realize the circuit, both of which are very intensive in the usage of vertical routing resources. Additionally, the topology requires both polarities of the clock for its operation. Realizing the requirements of the fabric, it is possible to create another flip-flop topology based on static flip-flop topology outlined in [1]. This flip-flop (Figure 1b) uses a single polarity of the clock and complex static gates. As such, the number of routing resources required is reduced. By selecting regular fabric friendly circuit topologies such as this one, it is therefore possible to increase transistor density and thus reduce the overall circuit area.
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Vyacheslav Rovner