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Jon Proesel Multi-GHz Flash ADC via Variation-Aware Analog Design Advisor: Larry Pileggi High-speed Flash Analog-to-Digital Converters (ADCs) are required in many practical applications, such as hard disk drive read channels, gigabit Ethernet receivers, and wireless receivers. To realize systemon- a-chip implementations of these applications, the flash ADC must be realized using modern deep-submicron CMOS processes. Flash ADCs become increasingly difficult to design in deep-submicron CMOS due to low supply voltages, low intrinsic gain, and large process variations. These difficulties impact ADC performance, limit resolution, degrade yield, and increase design effort. Therefore, modern flash ADC design must overcome device non-idealities and the large-scale process and environmental variations in order to avoid over-design, area and/or power penalty, or under-design, resulting in low product yield. In this project we propose and apply a number of novel techniques, e.g. reference centering, negative capacitance, statistical optimization, and regular analog fabrics, to achieve a robust, multi-GHz flash ADC design in 90nm CMOS technology. Selected Highlights Reference centering overcomes low gain and supply voltage issues to achieve good preamplifier gain across the full range of reference voltage (Vref) values in the flash ADC. In reference centering, the widths of a differential pair are deliberately mismatched, shifting the maximal gain point of the pair and allowing us to provide the optimal gain at any given Vref. This leads to a significant design challenge: each preamplifier has a different Vref, leading to 65 unique designs in the 6-bit case. Instead of producing 65 unique designs, a single regular analog fabric can be developed and configured for different Vref values. Using the variation-aware circuit optimizer ROAD, a regular analog fabric is designed which is robust over all process variations. Metal mask configurability is implemented over the fabric, preserving the robustness of the fabric. The overall design effort is greatly reduced, while the low gain is preserved to its maximal extent. The design flow is show in Figure 1. At Vref = 0.3V, the metal mask configured preamplifier has a gain 17 times better than the initial regular fabric design. A testchip for the regular analog fabric has been released in IBM 65nm technology. Matching requirements for accuracy force the use of large input transistors, which create a large input capacitance, limiting the input bandwidth. To recover bandwidth, a negative capacitance is created to cancel the large input capacitance. This negative capacitance is realized by positive capacitive feedback, creating a negative Miller capacitance. The use of positive feedback requires careful design that considers nonidealities such as bandwidth, peaking, and distortion. Using variation-aware analog design, gains in bandwidth can be achieved of up to 50% for power
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