 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Gokce Keskin Analysis and Control of IC Power Grids Advisors: Larry Pileggi and Xin Li Project With Shrinking supply voltages for today’s integrated circuits, maintaining the power supply voltage integrity within the required range of operation has become a critical design problem. Furthermore, as clock gating techniques are used to save power, a large portion of circuits are turned on/off simultaneously, which can introduce substantial transient switching noise to the power grid. The traditional solution for this problem is to include both on-chip and off-chip decoupling capacitors (100’s of nanofarads for on-chip decoupling is not uncommon) to reduce transient peaks by providing passive decoupling. Tighter noise margins in advanced processes require even more on-chip decoupling; however, with added capacitance, there is ultimately a diminishing return for adding more on-chip capacitance. This is particularly the case for nanoscale technologies when one considers not only the increase in area, but also the associated exponential increase in the leakage power for MOS capacitors. In this project we propose the use of active resistors for damping the typically underdamped power grid distribution to reduce both the amplitude and the duration of transient oscillations in the power/ground rails. Selected Highlights The circuit schematic for the proposed active resistor is shown in Figure1 (a). Compared with a traditional approach for damping using a passive resistor, our active resistor approach provides better damping effect with less power dissipation. Our active-R primarily consists of three blocks; a small-signal resistor, a gain stage and two transmission gates [1,2]. The gain stage helps achieve a smaller resistance value, hence better damping, with little power overhead. The transmission gates can be used to power down the active resistors when they are not required, and to activate them in anticipation of a gating signal. In Figure 1(b), an alternative way of implementing the resistors is shown with inclusion of a second higher supply voltage that can be used to improve the damping of the above-rail oscillations. Importantly, the proposed active resistor approach is extremely robust to manufacturing and environment variations. As with the original [2], this improved active resistor topology in Figure 1(b) was implemented in UMC’s 130nm CMOS technology. Post-layout simulations for the test chip design demonstrated a 68 % improvement in positive peaks and 36 % improvement in negative peaks over that with the original active-R design with lower settling time and no oscillations (Figure 2). The standby power of the active resistor is less then 5% of the total power consumption, and it can be placed in standby mode for further power saving.
References
|
Gokce Keskin
Sudhir Saini
