Thiago Hersan

Thiago Hersan

Statistical Optimization and Characterization of Regular Bricks

As CMOS technology continues to scale, pushing sub-wavelength lithography to its physical limits, greater geometric regularity of silicon patterns is required to guarantee circuit functionality, control process variations and achieve acceptable design quality. One specific methodology for building circuits from more restrictive structures leverages the concept of macro-regularity to group functions into a small set of pre-characterizable logic units called bricks [1]. Due to the small number of large functions, and since the bricks are built from a very micro-regular layout fabric [2], transistor-level optimization can provide not only a more efficient solution in terms of energy and delay, but hopefully more robust and predictable circuits as well. Since logic bricks contain a larger number of transistors and implement more complex functions when compared to the elements found in a standard cell library, being able to size individual transistors can usually lead to improvements in timing and energy. Unlike the discretely sized transistors used in standard cells, transistors that are internal to the bricks can be sized specifically for their load. In addition to taking advantage of a larger design space, brick sizing also offers a more predictable solution because internal routing can be extracted and taken into account during optimization. Even though the bricks are large enough to encompass a significant amount of logic, they are still small enough to be thoroughly modeled and characterized. Since most devices within a brick have well-defined neighborhoods, layout-specific systematic effects, like stress-induced mobility variation and diffusion rounding, can be accurately modeled and taken into account during optimization. Furthermore, statistical brick-specific transistor models, derived from the layout fabric, can then be used for brick optimization and characterization.

Selected Highlights

In this work a statistical, simulation-based, circuit optimization tool called ROAD [3] has been used to perform transistor sizing for the set of bricks used in the implementation of an ARM9 core. Figure 1 shows energy and delay comparisons between the original bricks, designed using elements from a standard cell library, and the final designs after ROAD optimization. Compared with the original designs, the optimized designs are able to reduce the energy-delay product by up to 10%. These bricks were also optimized using the available statistical models for generic transistors. While these models do not include any brickspecific statistical information, or layout dependent effects, they can be used to optimize the bricks to reduce performance variation due to variations in gate threshold voltage, effective gate length and width. Figure 2 shows the energy and delay probability density function for the original and optimized versions of one of the bricks. Both the mean and variance are reduced in this case.

Figure 1. Normalized Optimization Results Using Nominal Transistor Behavior.

Figure 2. Statistical Optimization Example.

References

1. V. Kheterpal, V. Rovner, T. Hersan, D. Motiani, Y. Takegawa, A. J. Strojwas and L. Pileggi, “Design Methodology For IC Manufacturability Based On Regular Logic-Bricks”, Proc. of the Design Automation Conference (DAC), June 2005.
2. T. Jhaveri, L. Pileggi, V. Rovner, and A. J. Strojwas, “Maximization Of Layout Printability/Manufacturability By Extreme Layout Regularity”, Proc. of SPIE Vol. 6156, March 2006.
3. X. Li, P. Gopalakrishnan, Y. Xu and L. Pileggi, “Robust Analog/RF Circuit Design With Projection-Based Posynomial Modeling”, Proc. of the International Conference on Computer Aided Design (ICCAD), November 2004. Figure 1. Normalized Optimization Results Using Nominal Transistor Behavior. Figure 2. Statistical Optimization Example. Circuits