Configurable SiGe CMOS RF LNA and Mixer Pairs Active Damping Circuit for Control of IC Power Grid Noise ARM926EJ implementation with all uni-directional patterning for poly, M1 and M2 in 65nm bulk CMOS Statistically optimized low noise amplifier in 130nm CMOS Flash ADC with Voltage Scaling to 0.6V in 90nm CMOS 90nm CMOS SRAM with Configurable Replica Bitline for Self Timing Sensitized Ring Oscillator Circuits for Process Monitoring of Individual Variations Comparison of statistical and corner-based optimization of 65nm sense amps.