Hamerschlag Hall, A-300 Wing, A9
Computer Architecture Lab (CALCM)
Department of Electrical & Computer Engineering
Carnegie Mellon University
5000 Forbes Ave
Pittbsurgh, PA 15213
Research
Memory Access Predictors (STeMS project page is here)
While memory capacity in recent years has increased commensurately with
processor speeds, memory speeds have primarily lagged behind. My research
focuses on mechanisms for a novel memory system that "proactively" moves
and places data among the cache hierarchy levels in anticipation of a
processor memory access, to hide the long memory latency. The key
mechanisms enabling proactive memory are memory access predictors that
monitor program execution, capture processor memory access patterns, and
accurately predict subsequent memory accesses.
Publications
Brian T. Gold, Michael Ferdman, Babak Falsafi, and Ken Mai, "Mitigating Multi-bit Soft Errors in L1 Caches Using Last Store Prediction," Workshop on Architectural Support for Gigascale Integration (ASGI-07), June 2007. (pdf)
Michael Ferdman and Babak Falsafi, "Last-Touch Correlated Data Streaming," Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007. (pdf)
Thomas F. Wenisch, Roland Wunderlich, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and James Hoe."SIMFLEX: Statistical Sampling of Computer System Simulation," IEEE MICRO Special Issue on Computer Architecture Simulation and Modeling, vol. 26, no. 4, July/August 2006. (pdf)
Thomas Zanon, Michael Ferdman, Kambiz Komeyli, and Wojciech P. Maly, "Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps (ISTFA)," Proceedings of the 30th Interational Symposium for Testing and Failure Analysis, November 2004. (pdf)
